Semi-conductor designs often contain both logic and memory circuits or contain different types of memory array circuits such as static RAMs (SRAMs) and dynamic RAMs (DRAMs). Typically, the circuit designs are "burned in" in a serial fashion; i.e., the logic circuits are burned in and then the memory circuits are burned in; or in the case of different types of memory, the static memory (SRAM) circuits are burned in and then the (DRAM) circuits are burned in. In the burn in of semi-conductor chips, the chips are stressed at elevated temperatures and voltages and various patterns are applied and sequences run for a period of time in a predetermined or preselected sequence. Typically, the patterns and sequences are generated by built-in self test logic referred to BIST and the engines for BIST devices are different for logic and memory and run significantly different patterns and sequences. Also, different engines are used for testing SRAMs and DRAMs contained on the same chip or in the same package. The voltages typically are about 1.1 times to 2.0 times operating voltage and these stress times typically range any where from 3 hours to 100 hours. Thus for each type of circuit there is a period of time required to perform the stress; and the cumulative stress times are significantly increased when the tests are run serially as has been the case in the past.
Thus it is an object of the present invention to provide an improved burn-in procedure for testing semi-conductor designs in which at least one type of circuit is tested by a BIST engines.